Digital logic circuitry is widely used in a variety of applications including computers, microprocessors, digital logic gate chips, controllers and other applications. In general electronic devices used in such applications can be improved by utilizing logic circuitry which is faster. Faster operation allows more electronic operations to be performed per second thus allowing the device to perform more functions and/or functions of higher sophistication and complexity.
A principal factor in speed limitation of digital logic circuitry is the operational switching speed of the switching transistors. The electronic processing of information in digital form requires numerous transistors to switch in various combinations, sequences and patterns in order to encode information into digital form and then to process such information using various analytical programs. Literally millions or even billions of transistor switching operations occur every second in many digital devices. The speed at which data is processed and analyzed depends on the combinational patterns and sequential progress of numerous transistor switches. Thus, any reduction in the period of time necessary to change or switch a transistor from a nonconductive or "off" state into a conductive or "on" state, or vice versa, can improve the overall speed of the digital system.
Many prior art digital logic families have suffered speed limitations due to electronic designs which cause the switching transistors to operate in a saturated mode in the conductive state. Saturation can be either partial or full depending on the bias voltage applied and other parameters of the circuit. In full or hard saturation, the base-collector diode junction becomes forward biased to a degree which overcomes the forward barrier voltage of the base-collector junction and causes substantial increase in base current. In silicon bipolar transistors hard saturation occurs when the base collector junction is forward biased more than approximately 650 millivolts (mV), assuming a base-emitter voltage of 800 mV when the transistor is on. This must be compared to typical non-saturated operational conditions in which the base-collector junction is reverse biased. Soft or partial saturation is where base current increases only a relatively small amount due to forward biasing of the base-collector junction. In silicon bipolar transistors soft saturation occurs between approximately 500-650 mV forward biasing on the base-collector junction. With base-collector forward biasing of less than approximately 500 mV the base current does not increase appreciably and the effects of this trivial saturation are minor. The other levels of saturation are significant bacause the switching speed of the transistors are slowed. Full saturation causes the longest switching times with increased speed as the degree of saturation decreases.
In order to prevent saturation some logic designs have employed clamping diodes which prevent a hard or full saturation from occurring by allowing drive current to bypass the base-collector junction when the transistor is turned on. Schottky diodes have been widely used for this purpose because their threshold voltage is lower than silicon diodes. Although use of such clamping or bypass constructions have improved performance, they have not provided switching speeds which fully utilize the high speed switching capabilities of bipolar transistors. Presently available logic families using such clamping techniques have similarly not achieved operational speeds which are commensurate with the speeds at which bipolar and other transistors can in fact operate.
Another problem area in digital logic circuitry includes variations in the voltages provided to different switching components spaced at different positions on the integrated circuit chip. This problem can be appreciated by considering the minute size of the conductors used to convey electrical current from one part of the integrated circuit to another. The small sizes of the conductors often cause significant variations in the voltage to occur depending on the current which the circuit is conducting. These changes in voltage along the conductor strips of integrated circuits require that relatively wide logic signal voltage ranges be accepted as defining a particular logic state. The voltages experienced over the power distribution system of an integrated circuit chip due to these and other causes thus has not been maintained with well defined values by prior art circuitry so as to allow minimum logic voltage swing or precise control of transistor biasing using the power supply lines. Most prior art logic families have allowed ground voltages to randomly vary across the chip due to use of a variety of interconnection patterns and conductor widths. This lack of control has maintained the need for gate decoupling diodes and/or clamp diodes or differential logic circuits with many additional bias devices. It has also been common to use relatively large conductor metal and have numerous power pins in order to help stabilize voltages for varying current flows.
Prior art logic circuitry also sometimes uses bias circuitry to set up operating voltages which are relatively independent of the power supply voltage. Emitter coupled logic (ECL) is a family which uses bias circuitry which is separate from the power supply for the transistors performing the logical switching operations. ECL also requires emitter followers between each gate to act as level shifters to eliminate saturation which would occur because the voltage swing must be large enough to overcome ground voltage drops. Due to the use of extra bias circuits and followers, ECL cannot operate on a low voltage power supply, such as less than 1 to 2 volts.
Logic families which utilizes low supply voltages, such as in the range of one volt, have greater potential for signal errors. Very accurate voltages are needed due to the exponential nature of the current output from a transistor, such as in a grounded emitter stage configuration. Utilization of the power supply voltage as a biasing or control circuit for the switching transistors in such circuitry is not acceptable because of the high degree of accuracy needed, both in absolute value and temperature tracking. Resistance of power leads on the chip causes voltage drops which make accurate biasing of low voltage logic circuits extremely difficult. One solution might be to use multiple local voltage regulators on the chip, such as used in nonthreshold logic (NTL). But regulators require extra voltage to operate, and can add as much power dissipation to the chip as the logic is already using. The regulators also add extra components. They further have a limited frequency response at the output and thus cannot adapt to rapidly changing current demands such as when the logic gates are switching. Large filter capacitors, which would stabilize switching transients, can only be used in off-chip regulators which unfortunately are rendered useless by the previously mentioned voltage drops in the chip metallization.
Another important consideration in integrated circuit design is the number of transistors needed to accomplish the various logical gates required for the particular digital circuitry being used. Chip manufactures seek to minimize the number of transistors in order to produce more chips per wafer, increase functional yield and speed, and use smaller chip packages. One early form of digital logic was termed direct coupled transistor logic (DCTL) which used only one transistor for the simplest logic element, an inverter. Unfortunately DCTL operated in a highly saturated mode which prevented high operating speeds.
DCTL also suffered from a phenomenon termed "current hogging" which occurred when the logical output of one switching transistor was connected to multiple subsequent stages, typically called "fanout". If the ground voltage for each of the subsequent stages was not matched then current tended to flow primarily in the subsequent stage having the lowest ground voltage, and one or more of the other transistors being controlled would not be properly activated. Thus current would not be evenly distributed between load transistors when they were turned on.
Another early logic family using a single transistor per inverter was resistor-transistor logic (RTL), which used grounded emitter transistors which had resistors between the logic inputs and the transistor bases. The resistors at the logical inputs reduced current hogging by decoupling the inputs but slowed response time. The input resistors did not satisfactorily solve the current distribution problem when building very large logic arrays, such as those which have hundreds or thousands of gates. The RTL logic also suffered substantial saturation problems and additional speed delay because of such saturation.
Other approaches to decoupling, such as diodes or transistors, will also slow switching speeds by increasing voltage swing and adding circuit nodes. Decoupling also consumes power and requires additional devices on the chip.
U.S. Pat. No. 4,165,470 assigned to Honeywell shows logic circuitry which utilizes a current source to feed the positive power network. A plurality of bipolar transistors receive logical inputs at their bases. The emitters are grounded to the negative network. The collectors are connected to load resistors which extends to the positive network. Each transistor turns on and conducts current through its load resistor to create a voltage drop across the load resistor which swings the next logic stage base low. The Honeywell circuits are forced to consistently use Schottky diodes to allow excess current from the driving transistor to shunt around the load resistor thus preventing hard saturation. However, the amount of shunted current varies depending on the logical code combination of the device at any particular time. The varying amounts of current must pass through the available transistors which are on, so the base-emitter bias voltage must fluctuate to accommodate the varying current. This leads to different biasing voltages for various logic states, which causes noise on the positive network, creates unpredictable and inconsistent delays in the gates due to transistor current variations, and causes the circuitry to operate more slowly than optimum due to the larger voltage swing needed to allow the Schottky diode to bypass excess current around the load resistor. Voltage drops on both the negative and positive networks also cause serious problems when attempting to build large logic arrays with the Honeywell logic.
Despite the fact that DCTL, RTL, NTL and the Honeywell logic families used only one resistors per input they were essentially abandoned in favor of other logic families having increased complexity in order to achieve greater speeds, predictable speeds, and/or reduced power consumption. I.sup.2 L, ISL, and STL are additional logic families which have problems with speed, speed variation, and noise immunity caused by supply line voltage drops, saturation, and logic code changes, especially with large arrays. Accordingly, there remains a need for a relatively simple, low cost logic circuitry which eliminates bias lines, bias circuits, clamp diodes, emitter followers, decoupling, voltage regulators, and their associated devices. It should operate reliably with a low and well controlled voltage swing, under non-saturating conditions, thus allowing high operating speeds. Such a desired circuitry will also utilize a low power supply voltage to achieve low power dissipation and thus allow higher functional density and operating speed.